CNN Accelerator on FPGA
A neural network, built out of silicon.
CNN inference as a parallel array of 16-bit multiply-accumulate units in Verilog, for edge devices where a GPU is not an option.
Built with
2025 · Hardware
What it does
Parallel array of 16-bit MAC units synthesised from Verilog RTL
Dataflow structured for weight and activation reuse per fetch
Fixed-point precision chosen against area and routing constraints
Targets real-time inference on a constrained power budget
The long version
Convolution is multiply-accumulate repeated at scale, which is exactly the shape an FPGA fabric is good at: instantiate hundreds of MAC units and feed them in parallel instead of serialising the same arithmetic through a CPU.
Arithmetic is fixed at 16 bits — enough precision to hold inference accuracy, small enough that the MAC array fits and routing stays feasible. The real constraint turns out not to be arithmetic at all but data movement, so the dataflow is structured to maximise weight and activation reuse per fetch.
The target is edge inference on devices where a GPU is out of the question: real-time classification inside a power budget an FPGA can actually meet.